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? 2011 semtech corporation 1 SC401B 15a integrated fet regulator with programmable ldo features power system input voltage 3v to 17v bias voltage 3v to 5.5v ldo or external up to 96% peak efciency integrated bootstrap switch programmable ldo output 200ma reference tolerance 1% t j = -40 to +125 c programmable soft-start time logic input/output control independent en controls for ldo and switcher programmable v in uvlo threshold power good output selectable psave or fcm mode protection over-voltage and under-voltage tc compensated r ds(on) sensed current limit thermal shutdown output capacitor types high esr sp, poscap, oscon ceramic capacitors package lead-free package 5x5mm, 32-pin mlpq rohs/weee compliant and halogen free applications networking and telecommunication equipment printers, dsl, and stb applications embedded systems and power supply modules point of load power supplies ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? description the SC401B is a stand-alone synchronous ecospeed tm buck power supply which incorporates semtechs advanced patented adaptive on-time control architecture. this pro - vides excellent light-load efficiency and fast transient response. it features integrated power mosfets, a boot - strap switch, and a programmable ldo in a 5x5mm package. the device is highly efcient and uses minimal pcb area. the SC401B has the same package and pin con - fguration as the entire sc40xb series for compatibility. the SC401B supports using standard capacitor types such as electrolytic or specialty polymer, in addition to ceramic, at switching frequencies up to 1mhz. the programmable frequency, synchronous operation, and selectable power save provide high efciency operation over a wide load range. additional features include a programmable soft-start, programmable cycle-by-cycle over-current limit protec - tion, under-voltage and over-voltage protection, soft shutdown, and selectable power save. the device also provides separate enable inputs for the pwm controller and ldo as well as a power good output for the pwm controller. the wide input range and programmable frequency make the device extremely fexible and easy to use in a broad range of applications. rev. 2.1 power management rton sc 401 b fb vout vdd vin ss bst pgnd lx pgood ilim lxs en / psv enl lxbst rilim cbst enable / psave enable ldo vext / ldo agnd + rfb 1 rfb 2 vout cout l 1 cin vin pgood ton 1 f csoft 10 ? typical application circuit
SC401B 2 pin confguration ordering information marking information sc 401 b yyww xxxxxx xxxxxx agnd pad 1 vin pad 2 lx pad 3 e n l 32 t o n 31 a g n d 30 e n / p s v 29 l x s 28 i l i m 27 p g o o d 26 l x 25 24 lx lx 23 pgnd 22 pgnd 21 pgnd 20 pgnd 19 pgnd 18 pgnd 17 p g n d 16 p g n d 15 l x b s t 13 v i n 11 v i n 10 v i n 9 bst 8 fbl 5 ss 7 vin 6 vdd 3 agnd 4 fb 1 top view vout 2 d h 12 d l 14 notes: 1) available in tape and reel only. a reel contains 3000 devices. 2) lead-free, halogen free, and rohs/weee compliant yyww = date code xxxxxx = semtech lot number xxxxxx = semtech lot number SC401B mlpq-32; 5x5, 32 lead device package SC401Bmltrt (1)(2) mlpq-32 5x5 SC401Bevb evaluation board
SC401B 3 absolute maximum ratings lx to pgnd (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +20 lx to pgnd (v) (transient 100ns max.) . . . . . . -2 to +20 vin to pgnd (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +20 vin to vdd (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4 en/psv, pgood, ilim, to gnd (v) . . . . . -0.3 to +(vdd + 0.3) ss, vout, fb, fbl, to gnd (v) . . . . . . . . . -0.3 to +(vdd + 0.3) vdd to pgnd (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6 ton to pgnd (v) . . . . . . . . . . . . . . . . . . . . . -0.3 to +(vdd - 1.5) enl (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to v in dh, bst to lx (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 dh, bst to pgnd (v) . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +25 dl to pgnd (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 agnd to pgnd (v) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3 esd protection level (1) (kv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 recommended operating conditions input voltage (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 to 17 vdd to pgnd (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 to 5.5 vout to pgnd (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 to 5.5 thermal information storage temperature (c) . . . . . . . . . . . . . . . . . . . . -60 to +150 maximum junction temperature (c) . . . . . . . . . . . . . . . 150 operating junction temperature (c) . . . . . . -40 to +125 thermal resistance, junction to ambient (2) (c/w) high-side mosfet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 low-side mosfet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 pwm controller and ldo thermal resistance . . . . . 50 peak ir refow temperature (c) . . . . . . . . . . . . . . . . . . . . 260 exceeding the above specifcations may result in permanent damage to the device or device malfunction. operation outside of the parameters specifed in the electrical characteristics section is not recommended. notes: (1) tested according to jedec standard jesd22-a114. (2) calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer fr4 pcb with thermal vias under the exposed pad per jesd51 standards. unless specifed: v in =12v, t a = +25c for typ, -40 to +85 c for min and max, t j < 125c, vdd = +5v, typical application circuit electrical characteristics parameter conditions min typ max units input supplies input supply voltage v in > vdd 3 17 v vdd voltage 3 5.5 v vin uvlo threshold (1) sensed at enl pin, rising edge 2.40 2.60 2.95 v sensed at enl pin, falling edge 2.23 2.40 2.57 vin uvlo hysteresis en/psv = high 0.25 v vdd uvlo threshold measured at vdd pin, rising edge 2.5 3.0 v measured at vdd pin, falling edge 2.4 2.9 vdd uvlo hysteresis 0.2 v vin supply current enl , en/psv = 0v, v in = 20v 10 20 a standby mode; enl=vdd, en/psv = 0v 130
SC401B 4 electrical characteristics (continued) parameter conditions min typ max units input supplies (continued) vdd supply current enl , en/psv = 0v, no external 5v vdd 3 7 a enl , en/psv = 0v, external 5v vdd supply 190 300 en/psv = vdd (psave), no load, vfb > 600mv 0.7 vdd = 5v, f sw = 250khz, en/psv = foating , no load (2) 9 ma vdd = 3v, f sw = 250khz, en/psv = foating , no load (2 5.5 fb on-time threshold static v in and load, t j = 0 to +125 c 0.595 0.6 0.605 v static v in and load, t j = -40 to +125 c 0.594 0.6 0.606 v frequency range continuous mode operation 1000 khz bootstrap switch resistance 10 ? timing on-time continuous mode operation, v in = 12v, v out = 5v, f sw = 300khz, r ton = 133k? 999 1110 1220 ns minimum on-time (2) 80 ns minimum of-time (2) vdd = 5v 250 ns vdd = 3.3v 370 soft-start soft-start current 3.0 a soft-start voltage (2) when v out reaches regulation 1.5 v analog inputs/outputs vout input resistance 500 k? current sense zero-crossing detector threshold lx - pgnd -3 0 +3 mv power good power good threshold upper limit, v fb > internal 600mv reference +20 % lower limit, v fb < internal 600mv reference -10 % start-up delay time (between pwm enable and pgood high) vdd = 5v, c ss = 10nf 12 ms vdd = 3.3v, c ss = 10nf 7
SC401B 5 electrical characteristics (continued) parameter conditions min typ max units power good (continued) power good start-up delay threshold on ss pin ss voltage when pgood goes high 64 %vdd fault (noise immunity) delay time (2) 5 s leakage 1 a power good on-resistance 10 ? fault protection valley current limit (3) vdd = 5v, r ilim = 7150 , t j = 0 to +125 c 13.5 15 16.5 a vdd = 3.3v, r ilim = 7150 13.5 a i lim source current 10 a i lim comparator ofset with respect to agnd -10 0 +10 mv output under-voltage fault v fb with respect to internal 600 mv reference, 8 consecutive clocks -25 % smart power save protection threshold (2) v fb with respect to internal 600 mv reference +10 % over-voltage protection threshold v fb with respect to internal 600 mv reference +20 % over-voltage fault delay (2) 5 s over-temperature shutdown (2) 10 c hysteresis 150 c logic inputs/outputs logic input high voltage enl 1.0 v logic input low voltage enl 0.4 v en/psv input for psave operation (2) vdd = 5v 2.2 5 v en/psv input for forced continuous operation (2) 1 2 v en/psv input for disabling switcher 0 0.4 v en/psv input bias current en/psv= vdd or agnd -10 +10 a enl input bias current enl = v in = 20v 10 18 a fbl, fb input bias current fbl, fb = vdd or agnd -1 +1 a
SC401B 6 electrical characteristics (continued) parameter conditions min typ max units linear regulator (ldo) fbl accuracy vldo load = 5ma 0.728 0.75 0.773 v ldo current limit short-circuit protection, v in = 12v, v dd < 0.75v 65 ma start-up and foldback, v in = 12v, 0.75 < v dd < 90% of fnal v dd value 115 operating current limit, v in = 12v, v dd > 90% of fnal v dd value 135 200 vldo to vout switch-over threshold (4) -130 +130 mv vldo to vout non-switch-over threshold (4) -500 +500 mv vldo to vout switch-over resistance v out = +5v 2 ? ldo drop out voltage (5) from v in to v dd , v dd = +5v, i vldo = 100ma 1.2 v notes: (1) v in uvlo is programmable using a resistor divider from vin to enl to agnd. the enl voltage is compared to an internal reference. (2) typical value measured on standard evaluation board. (3) SC401B has frst order temperature compensation for over current. results vary based upon the pcb thermal layout. (4) the switch-over threshold is the maximum voltage diferential between the vdd and vout pins which ensures that vldo will internally switch-over to vout. the non-switch-over threshold is the minimum voltage diferential between the vldo and vout pins which ensures that vldo will not switch-over to vout. (5) the ldo drop out voltage is the voltage at which the ldo output drops 2% below the nominal regulation point.
SC401B 7 rton 130 k ? sc 401 b fb 1 vout 2 vdd 3 agnd 4 fbl 5 vin 6 ss 7 bst 8 v i n 9 v i n 1 0 v i n 1 1 p g n d 1 5 p g n d 1 6 17 18 19 20 21 pgnd 22 lx 23 lx 24 l x 2 5 p g o o d 2 6 i l i m 2 7 l x s 2 8 e n / p s v 2 9 a g n d 3 0 t o n 3 1 e n l 3 2 d l 1 4 l x b s t 1 3 1 2 v i n p a d 2 agnd pad 1 lx pad 3 rilim 7 . 68 k ? rldo 2 75 k ? rldo 1 422 k ? cin 2 x 10 f ( see note ) rgnd 0 cbst 1 f vin + 12 v pgnd pgnd pgnd pgnd pgnd cff 100 pf rfb 1 10 k ? l 1 1 h rfb 2 6 . 65 k ? vout 1 . 5 v @ 15 a , 300 khz enable / psave enable ldo + cout 7 . 5 m ? 2 x 220 f pgood 1 f component value manufacturer part number web cin ( see note ) 2 x 10 f / 25 v murata grm 32 dr 71 e 106 ka 12 l www . murata . com www . edc . sanyo . com key components note : the quantity of 10 f input capacitors required varies with the application requirements . www . cyntec . com internal ldo used as bias 3 . 3 nf 2 . 2 f 1 f cout 2 x 220 f / 15 m ? sanyo 4 tpe 220 mf pimb 104 t - 1 r 0 ms 1 . 0 h / 3 m ? cyntec l 1 d h rbst 3 . 3 ? detailed application circuit-1
SC401B 8 rton 130 k ? sc 401 b fb 1 vout 2 vdd 3 agnd 4 fbl 5 vin 6 ss 7 bst 8 v i n 9 v i n 1 0 v i n 1 1 p g n d 1 5 p g n d 1 6 17 18 19 20 21 pgnd 22 lx 23 lx 24 l x 2 5 p g o o d 2 6 i l i m 2 7 l x s 2 8 e n / p s v 2 9 a g n d 3 0 t o n 3 1 e n l 3 2 d l 1 4 l x b s t 1 3 d h 1 2 v i n p a d 2 agnd pad 1 lx pad 3 rilim 7 . 68 k ? 5 v 10 ? cin 2 x 10 f ( see note ) rgnd 0 cbst 1 f vin + 12 v pgnd pgnd pgnd pgnd pgnd cff 100 pf rfb 1 10 k ? l 1 1 h rfb 2 6 . 65 k ? vout 1 . 5 v @ 15 a , 300 khz enable / psave + cout 7 . 5 m ? 2 x 330 f pgood 1 f component value manufacturer part number web cin ( see note ) 2 x 10 f / 25 v murata grm 32 dr 71 e 106 ka 12 l www . murata . com www . edc . sanyo . com key components note : the quantity of 10 f input capacitors required varies with the application requirements . www . cyntec . com external 3 . 3 v - 5 v used as bias 3 . 3 nf 2 . 2 f 1 f cout 2 x 220 f / 15 m ? sanyo 4 tpe 220 mf pimb 104 t - 1 r 0 ms 1 . 0 h / 3 m ? cyntec l 1 rbst 3 . 3 ? detailed application circuit-2
SC401B 9 typical characteristics efciency/power loss vs. load psave 50 55 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 i out (a ) efficiency (%) 0.0 1.0 2.0 3.0 4.0 5.0 ploss (w) v in = 5 v v in = 5 v v in = 17 v v in = 17 v p loss efficiency v in = 12 v v in = 12 v characteristics in this section are based on using the typical application circuit on page 8. 50 55 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 i out (a ) efficiency (%) -0.0250 0.0075 0.0400 0.0725 0.1050 0.1375 0.1700 0.2025 0.2350 0.2675 0.3000 p loss (w) fcm minus psm fcm psave 50 55 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 i out (a ) efficiency (%) -0.0500 -0.0175 0.0150 0.0475 0.0800 0.1125 0.1450 0.1775 0.2100 0.2425 0.2750 p loss (w) fcm minus psm fcm psave 50 55 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 i out (a ) efficiency (%) 0.0 1.0 2.0 3.0 4.0 5.0 power loss (w) v in = 17 v v in = 17 v v in = 5 v v in = 5 v v in = 12 v v in = 12 v p loss efficiency 50 55 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 i out (a ) efficiency (%) 0.0 1.0 2.0 3.0 4.0 5.0 p loss (w) v in = 5 v v in = 5 v v in = 17 v v in = 17 v p loss efficiency v in = 12 v v in = 12 v 50 55 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 i out (a ) efficiency (%) -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0.25 0.30 p loss (w) 3 . 3 v bias 5 v bias 3 . 3 v minus 5 v efciency/power loss vs. load psave efciency/power loss vs. load fcm efciency/power loss psave vs. fcm efciency/power loss psave vs. fcm efciency/power loss psave vdd = 3.3v, v out = 1.5v vdd = 5v, v out = 1.5v vdd = 5v, v out = 1.5v vdd = 3.3v, v out = 1.5v, v in = 12v vdd = 5v, v out = 1.5v, v in = 12v v out = 1.5v, v in = 12v
SC401B 10 typical characteristics (continued) load regulation fcm 1.505 1.510 1.515 1.520 1.525 1.530 1.535 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 i out (a ) vout (v) v in = 5 v v in = 12 v characteristics in this section are based on using the typical application circuit on page 8. 1.505 1.510 1.515 1.520 1.525 1.530 1.535 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 i out (a ) vout (v) v in = 5 v v in = 12 v 0 50 100 150 200 250 300 350 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 i out ( a ) s w i t c h i n g f r e q u e n c y ( k h z ) fcm psave load regulation fcm load regulation psave load regulation psave switching frequency psave mode vs. fcm switching frequency psave vs. fcm vdd = 5v, v out = 1.5v vdd = 5v, v out = 1.5v vdd = 5v, v out = 1.5v, v in = 12v 1.505 1.510 1.515 1.520 1.525 1.530 1.535 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 i out (a ) vout (v) v in = 5 v v in = 12 v vdd = 3.3v, v out = 1.5v 1.505 1.510 1.515 1.520 1.525 1.530 1.535 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 i out (a ) vout (v) v in = 5 v v in = 12 v vdd = 3.3v, v out = 1.5v 0 50 100 150 200 250 300 350 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 i out ( a ) s w i t c h i n g f r e q u e n c y ( k h z ) vdd = 3.3v, v out = 1.5v, v in = 12v
SC401B 11 typical characteristics (continued) load regulation vs. temperature fcm 1.505 1.510 1.515 1.520 1.525 1.530 1.535 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 i out (a ) vout (v) t a = 25 c v in = 5 v t a = - 40 c v in = 5 v t a = 85 c v in = 5 v t a = 85 c v in = 12 v t a = - 40 c v in = 12 v t a = 25 c v in = 12 v characteristics in this section are based on using the typical application circuit on page 8. 1.505 1.510 1.515 1.520 1.525 1.530 1.535 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 i out (a ) vout (v) t a = - 40 c v in = 5 v t a = 25 c v in = 5 v t a = 85 c v in = 5 v t a = 85 c v in = 12 v t a = - 40 c v in = 12 v t a = 25 c v in = 12 v load regulation vs. temperature fcm load regulation vs. temperature psave load regulation vs. temperature psave efciency variation with v out psave vdd = 5v, v out = 1.5v 1 . 505 1 . 510 1 . 515 1 . 520 1 . 525 1 . 530 1 . 535 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 i out ( a ) v o u t ( v ) t a = - 40 c v in = 5 v t a = 25 c v in = 5 v t a = 85 c v in = 5 v t a = 85 c v in = 12 v t a = - 40 c v in = 12 v t a = 25 c v in = 12 v vdd = 3.3v, v out = 1.5v vdd = 5v, v out = 1.5v 1.505 1.510 1.515 1.520 1.525 1.530 1.535 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 i out (a ) vout (v) t a = - 40 c v in = 5 v t a = 25 c v in = 5 v t a = 85 c v in = 5 v t a = 85 c v in = 12 v t a = - 40 c v in = 12 v t a = 25 c v in = 12 v vdd = 3.3v, v out = 1.5v 75 80 85 90 95 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 i out ( a ) e f f i c i e n c y ( % ) v out = 2 . 5 v v out = 5 v v out = 1 v v out = 1 . 5 v v out = 3 . 3 v vdd = 5v, v in = 12v, l = 2.2uh (4.6m ?) for v out = 2.5v, 3.3v and 5v 50 55 60 65 70 75 80 85 90 95 100 0.000 0.001 0.010 0.100 1.000 10.000 100.000 i out (a ) efficiency (%) 0.00 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 p loss (w) external bias ldo bias ldo minus external efciency/power loss psave v out = 1.5v, v in = 12v
SC401B 12 start-up en/psv time (1m s/div) s/div) /div) (5v/div) (1v/div) (500mv/div) (5v/div) vdd = 5v, v in = 12v, v out = 1.5v, i out = 0a typical characteristics (continued) characteristics in this section are based on using the typical application circuit on page 8. shutdown en/psv time (20 s/div) s/div) /div) (5v/div) (2v/div) (500mv/div) (5v/div) vdd = 5v, v in = 12v, v out = 1.5v, i out = 5a power save mode time (10m s/div) s/div) /div) (50mv/div) (5v/div) vdd = 5v, v in = 12v, v out = 1.5v, i out = 0a forced continuous mode time (5 s/div) s/div) /div) (50mv/div) (5v/div) vdd = 5v, v in = 12v, v out = 1.5v, i out = 15a over current protection under-voltage protection time (100 s/div) s/div) /div) (5v/div) (500mv/div) (5a/div) (5v/div) vdd = 5v, v in = 12v, v out = 1.5v start-up (pre-bias) en/psv time (1 m s/div) s/div) /div) (5v/div) (2v/div) (500mv/div) (5v/div) vdd = 5v, v in = 12v, v out = 1.5v, i out = 0a 2.2ms 20.9a 15.5a
SC401B 13 typical characteristics (continued) characteristics in this section are based on using the typical application circuit on page 8. rising edge (deadtime) lx, dl time (10n s/div) s/div) /div) (1v/div) vdd = 5v, v in = 12v, v out = 1.5v, i out = 15a transient response psave load rising time (10 s/div) s/div) /div) (5a/div) (50mv/div) (5v/div) vdd = 5v, v in = 12v, v out = 1.5v, i out = 1a to 11a, di/dt = 1a/ s s falling edge (deadtime) lx, dl time (10n s/div) s/div) /div) (1v/div) vdd = 5v, v in = 12v, v out = 1.5v, i out = 15a transient response fcm time (20 s/div) s/div) /div) (5a/div) (50mv/div) (5v/div) vdd = 5v, v in = 12v, v out = 1.5v, i out = 5a to 15a, di/dt = 1a/ s s transient response psave load falling time (10 s/div) s/div) /div) (5a/div) (50mv/div) (5v/div) vdd = 5v, v in = 12v, v out = 1.5v, i out = 11a to 1a, di/dt = 1a/ s s over temperature shutdown 159 o c time (500 s/div) s/div) /div) (10v/div) (2v/div) v in = 12v, v out = 1.5v, i out = 0a, ldo mode 16ns 13ns (1v/div) (1v/div) 70mv
SC401B 14 pin descriptions pin # pin name pin function 1 fb feedback input for switching regulator used to program the output voltage connect to an external resis - tor divider from vout to agnd. 2 vout switcher output voltage sense pin also the input to the internal switch-over between vout and vldo. the voltage at this pin must be less than or equal to the voltage at the vdd pin. 3 vdd bias supply for the ic when using the internal ldo as a bias power supply, vdd is the ldo output. when using an external power supply as the bias for the ic, the ldo output should be disabled. 4, 30, pad 1 agnd analog ground 5 fbl feedback input for the internal ldo connect to an external resistor divider from vdd to agnd used to program the ldo output. 6, 9-11, pad 2 vin input supply voltage 7 ss the soft start ramp will be programmed by an internal current source charging a capacitor on this pin. 8 bst bootstrap pin connect a capacitor of at least 100nf from bst to lx to develop the foating supply for the high-side gate drive. 12 dh high-side gate drive 13 lxbst lx boost connect to the bst capacitor. 23-25, pad 3 lx switching (phase) node 14 dl low-side gate drive 15-22 pgnd power ground 26 pgood open-drain power good indicator high impedance indicates power is good. an e xternal pull-up resistor is required. 27 ilim current limit sense pin used to program the current limit by connecting a resistor from ilim to lxs. 28 lxs lx sense connects to r ilim . 29 en/psv enable/power save input for the switching regulator connect to agnd to disable the switching regulator, connect to vdd to operate with power save mode and foat to operate in forced continuous mode. 31 ton on-time programming input set the on-time by connecting through a resistor to agnd 32 enl enable input for the ldo connect enl to agnd to disable the ldo. drive with logic signal for logic con - trol, or program the vin uvlo with a resistor divider between vin, enl, and agnd.
SC401B 15 block diagram reference soft start fb agnd on - time generator control & status pgood gate drive control vin pgnd ton vout zero cross detector valley current limit ilim enl fbl vldo switchover mux a y b ldo vdd bst fb comparator - lx en / psv bypass comparator bypass comparator dh dl a 12 8 27 14 32 5 3 2 31 1 26 29 a = connected to pins 6 , 9 - 11 , pad 2 b = connected to pins 23 - 25 , pad 3 c = connected to pins 15 - 22 d = connect to pins 4 , 30 , pad 1 b c d v in vdd vdd v in bootstrap switch lo - side mosfet hi - side mosfet lxbst 13 lxs 28 dl dl vdd vdd vdd ss 7
SC401B 16 synchronous buck converter the SC401B is a step down synchronous dc-dc buck converter with integrated power mosfets and a 200ma capable programmable ldo. the device is capable of 15a operation at very high efciency. a space saving 5x5 (mm) 32-pin package is used. the programmable operating frequency of up to 1mhz enables optimizing the confgu - ration for pcb area and efciency. the buck controller uses a pseudo-fxed frequency adap - tive on-time control. this control method allows fast tran - sient response which permits the use of smaller output capacitors. in addition to the following information, the user can click on the applicable link to go to the SC401B online c-sim design and simulation too l , which will lead the user through the design process. input voltage requirements the SC401B requires two input supplies for normal opera - tion: v in and vdd. v in operates over a wide range from 3v to 17v. vdd requires a 3v to 5.5v supply input that can be an external source or the internal ldo configured to supply 3v to 5.5v from v in . power up sequence when the SC401B uses an external power source at the vdd pin, the switching regulator initiates the start up when v in , vdd and en/psv are above their respective thresholds. when en/psv is at a logic high, vdd needs to be applied after v in rises. also, it is recommended to use a 10? resistor between an external power source and the vdd pin. to start up by using the en/psv pin when both vdd and v in are above their respective thresholds, apply en/psv to enable the start-up process. for SC401B in self-biased mode, refer to the ldo section for a full description. shutdown the SC401B can be shut down by pulling either vdd or en/psv below its threshold. when using an external power source, it is recommended that the vdd voltage ramps down before the v in voltage. when vdd is active and en/psv at low logic, the output voltage discharges through an internal fet. psuedo-fxed frequency adaptive on-time control the pwm control method used by the SC401B is pseudo- fxed frequency, adaptive on-time, as shown in figure 1. the ripple voltage generated at the output capacitor esr is used as a pwm ramp signal. this ripple is used to trigger the on-time of the controller. q 1 q 2 l c out esr + c in v out fb threshold v fb v lx v lx ton fb v in figure 1 pwm control method, v out ripple the adaptive on-time is determined by an internal one- shot timer. when the one-shot is triggered by the output ripple, the device sends a single on-time pulse to the high- side mosfet. the pulse period is determined by v out and v in ; the period is proportional to output voltage and inversely proportional to input voltage. with this adaptive on-time arrangement, the device automatically antici - pates the on-time needed to regulate v out for the present v in condition and at the selected frequency. the advantages of adaptive on-time control are: predictable operating frequency compared to other variable frequency methods reduced component count by eliminating the error amplifer and compensation components reduced component count by removing the need to sense and control inductor current fast transient response the response time is controlled by a fast comparator instead of a typi - cally slow error amplifer. reduced output capacitance due to fast tran - sient response ? ? ? ? ? applications information
SC401B 17 one-shot timer and operating frequency the one-shot timer operates as shown in figure 2. the fb comparator output goes high when v fb is less than the internal 600mv reference. this feeds into the gate drive and turns on the high-side mosfet, and also starts the one-shot timer. the one-shot timer uses an internal com - parator and a capacitor. one comparator input is con - nected to v out , the other input is connected to the capacitor. when the on-time begins, the internal capaci - tor charges from zero volts through a current which is proportional to v in . when the capacitor voltage reaches v out , the on-time is completed and the high-side mosfet turns of. gate drives fb comparator one - shot timer on - time = k x r ton x ( v out / v in ) v out v in fb v ref q 1 q 2 l c out v in esr + v out v lx fb dh dl r ton + - figure 2 on-time generation this method automatically produces an on-time that is proportional to v out and inversely proportional to v in . under steady-state conditions, the switching frequency can be determined from the on-time by the following equation. in on out sw v t v f u the SC401B uses an external resistor to set the on-time which indirectly sets the frequency. the on-time can be programmed to provide an operating frequency up to 1mhz using a resistor between the ton pin and ground. the resistor value is selected by the following equation. sw ton f pf 25 k r u the constant, k, equals 1 when vdd is greater than 3.6v. if vdd is less than 3.6v and v in is greater than (vdd -1.75) x 10, k is shown by the following equation. the maximum r ton value allowed is shown by the follow - ing equation. a 15 v r min _ in max _ ton p v out voltage selection the switcher output voltage is regulated by comparing v out as seen through a resistor divider at the fb pin to the internal 600mv reference voltage, see figure 3. r 1 to fb pin r 2 v out figure 3 output voltage selection note that this control method regulates the valley of the output ripple voltage, not the dc value. the dc output voltage v out is ofset by the output ripple according to the following equation. ? 1 ? ? ? 1 ? u 2 v r r 1 6 . 0 v ripple 2 1 out when a large capacitor is placed in parallel with r 1 (c top ) v out is shown by the following equation. 2 top 1 2 1 2 2 top 1 ripple 2 1 out c r r r r 1 ) c r ( 1 2 v r r 1 6 . 0 v ? ? 1 ? z u z u ? 1 ? ? ? 1 ? u enable and power save inputs the en/psv input is used to enable or disable the switch - ing regulator. when en/psv is low (grounded), the switch - ing regulator is of and in its lowest power state. when of, the output of the switching regulator soft-discharges the output into a 15? internal resistor via the vout pin. when en/psv is allowed to foat, the pin voltage will foat to 33% of the voltage at vdd. the switching regulator turns on with power save disabled and all switching is in forced continuous mode. when en/psv is high (above 44% of the voltage at vdd), the switching regulator turns on with power save enabled. applications information (continued) in v 10 75 . 1 vdd k u
SC401B 18 the SC401B power save operation maintains a minimum switching frequency of 25khz, for applications with strin - gent audio requirements. forced continuous mode operation the SC401B operates the switcher in fcm (forced continuous mode) by foating the en/psv pin (see figure 4). in this mode one of the power mosfets is always on, with no intentional dead time other than to avoid cross- conduction. this feature results in uniform frequency across the full load range with the trade-of being poor efciency at light loads due to the high-frequency switch - ing of the mosfets. dh is gate signal to drive upper mosfet. dl is lower gate signal to drive lower mosfet. fb ripple voltage ( v fb ) fb threshold dl dh inductor current dc load current dh on - time is triggered when v fb reaches the fb threshold . on - time ( t on ) dl drives high when on - time is completed . dl remains high until v fb falls to the fb threshold . figure 4 forced continuous mode operation power save operation the SC401B provides power-save operation at light loads with no minimum operating frequency. with power-save enabled, the internal zero crossing comparator monitors the inductor current via the voltage across the low-side mosfet during the of-time. if the inductor current falls to zero for 8 consecutive switching cycles, the controller enters power-save operation. it will turn of the low-side mosfet on each subsequent cycle provided that the current crosses zero. at this time both mosfets remain of until v fb drops to the 600mv threshold. because the mosfets are off, the load is supplied by the output capacitor. if the inductor current does not reach zero on any switch - ing cycle, the controller immediately exits power-save and returns to forced continuous mode. figure 5 shows power-save operation at light loads. fb ripple voltage ( v fb ) fb threshold dl dh inductor current zero ( 0 a ) dh on - time is triggered when v fb reaches the fb threshold . on - time ( t on ) dl drives high when on - time is completed . dl remains high until inductor current reaches zero . dead time varies according to load figure 5 power save operation smart power save protection active loads may leak current from a higher voltage into the switcher output. under light load conditions with power save enabled, this can force v out to slowly rise and reach the over-voltage threshold, resulting in a hard shut - down. smart power save prevents this condition. when the fb voltage exceeds 10% above nominal, the device immediately disables power save, and dl drives high to turn on the low-side mosfet. this draws current from v out through the inductor and causes v out to fall. when v fb drops back to the 600mv trip point, a normal t on switch - ing cycle begins. this method prevents a hard ovp shut - down and also cycles energy from v out back to v in . it also minimizes operating power by avoiding forced conduc - applications information (continued)
SC401B 19 tion mode operation. figure 6 shows typical waveforms for the smart power save feature. smartdrive tm for each dh pulse the dh driver initially turns on the high- side mosfet at a lower speed, allowing a softer, smooth turn-of of the low-side diode. once the diode is of and the lx voltage has risen 0.5v above pgnd, the smartdrive circuit automatically drives the high-side mosfet on at a rapid rate. this technique reduces switching losses while maintaining high efciency and also avoids the need for snubbers or series resistors in the gate drive. fb threshold high - side drive ( dh ) low - side drive ( dl ) v out drifts up to due to leakage current flowing into c out dh and dl off dl turns on when smart psave threshold is reached smart power save threshold dl turns off when fb threshold is reached single dh on - time pulse after dl turn - off v out discharges via inductor and low - side mosfet normal dl pulse after dh on - time pulse normal v out ripple figure 6 smart power save current limit protection the device features programmable current limiting, which is accomplished by using the rds on of the lower mosfet for current sensing. the current limit is set by r ilim resistor. the r ilim resistor connects from the ilim pin to the lxs pin which is also the drain of the low-side mosfet. when the low-side mosfet is on, an internal ~10 a current fows from the ilim pin and through the r ilim resistor, creating a voltage drop across the resistor. while the low-side mosfet is on, the inductor current fows through it and creates a voltage across the rds on . the voltage across the mosfet is negative with respect to ground. if this mosfet voltage drop exceeds the voltage across r ilim , the voltage at the ilim pin will be negative and current limit will acti - vate. the current limit then keeps the low-side mosfet on and will not allow another high-side on-time, until the current in the low-side mosfet reduces enough to bring the ilim voltage back up to zero. this method regulates the inductor valley current at the level shown by ilim in figure 7. time i peak i load i lim i n d u c t o r c u r r e n t figure 7 valley current limit setting the valley current limit to 15a results in a peak inductor current of 15a plus peak ripple current. in this situation, the average (load) current through the inductor is 15a plus one-half the peak-to-peak ripple current. the internal 10 a current source is temperature compen - sated at 4100ppm in order to provide tracking with the rds on . the r ilim value is calculated by the following equation. r ilim = 495 x i lim x [0.0647 x (5v - vdd) +1] when selecting a value for r ilim be sure not to exceed the absolute maximum voltage value for the ilim pin. note that because the low-side mosfet with low rds on is used for current sensing, the pcb layout, solder connections, and pcb connection to the lx node must be done care - fully to obtain good results. r ilim should be connected directly to lxs (pin 28). soft-start of pwm regulator SC401B has a programmable soft-start time that is con - trolled by an external capacitor at the ss pin. after the controller meets both uvlo and en/psv thresholds, the controller has an internal current source of 3a fowing through the ss pin to charge the capacitor. during the applications information (continued)
SC401B 20 start up process (figure 8), 40% of the voltage at the ss pin is used as the reference for the fb comparator. the pwm comparator issues an on-time pulse when the voltage at the fb pin is less than 40% of the ss pin. as a result, the output voltage follows the ss voltage. the output voltage reaches and maintains regulation when the soft start voltage is > 1.5v. the time between the frst lx pulse and v out reaching regulation is the soft-start time (t ss ). the calculation for the soft-start time is shown by the following equation. a 3 v 5 . 1 c t ss ss p u the voltage at the ss pin continues to ramp up and eventu - ally equals 64% of v dd . after the soft start completes, the fb pin voltage is compared to an internal reference of 0.6v. the delay time between the v out regulation point and pgood going high is shown by the following equation. a 3 ) v 5 . 1 v 64 . 0 ( c t dd ss delay - pgood p u u figure 8 soft-start timing diagram pre-bias startup the SC401B can start up normally even when there is an existing output voltage present. the soft start time is still the same as normal start up (when the output voltage starts from zero). the output voltage starts to ramp up when 40% of the voltage at ss pin meets the existing fb voltage level. pre-bias startup is achieved by turning of the lower gate when the inductor current falls below zero. this method prevents the output voltage from discharging. power good output the pgood (power good) output is an open-drain output which requires a pull-up resistor. when the voltage at the fb pin is 10% below the nominal voltage, pgood is pulled low. it is held low until the output voltage returns above -8% of nominal. pgood will transition low if the v fb pin exceeds +20% of nominal, which is also the over-voltage shutdown thresh - old. pgood also pulls low if the en/psv pin is low when vdd is present. output over-voltage protection over-voltage protection becomes active as soon as the device is enabled. the threshold is set at 600mv + 20% (720mv). when v fb exceeds the ovp threshold, dl latches high and the low-side mosfet is turned on. dl remains high and the controller remains of, until the en/psv input is toggled or vdd is cycled. there is a 5s delay built into the ovp detector to prevent false transitions. pgood is also low after an ovp event. output under-voltage protection when v fb falls 25% below its nominal voltage (falls to 450mv) for eight consecutive clock cycles, the switcher is shut of and the dh and dl drives are pulled low to tri- state the mosfets. the controller stays of until en/psv is toggled or vdd is cycled. vdd uvlo, and por uvlo (under-voltage lock-out) circuitry inhibits switching and tri-states the dh/dl drivers until vdd rises above 3v. an internal por (power-on reset) occurs when vdd exceeds 3v, which resets the fault latch and a soft-start counter cycle begins which prepares for soft-start. the SC401B then begins a soft-start cycle. the pwm will shut of if vdd falls below 2.4v. applications information (continued)
SC401B 21 ldo regulator SC401B has an option to bias the switcher by using an internal ldo from v in . the ldo output is connected to vdd internally. the output of the ldo is programmable by using external resistors from the vdd pin to agnd (see figure 9). the feedback pin (fbl) for the ldo is regulated to 750mv. vdd to fbl pin r ldo 2 r ldo 1 figure 9 ldo output voltage selection the ldo output voltage is set by the following equation. ? ? 1 ? u 2 ldo 1 ldo r r 1 mv 750 vldo a minimum capacitance of 1f referenced to agnd is normally required at the output of the ldo for stability. note that if the ldo voltage is set lower than 4.5v, the minimum output capacitance for the ldo is 10uf. ldo enl functions the enl input is used to enable/disable the internal ldo. when enl is a logic low, the ldo is of. when enl is above the vin uvlo threshold, the ldo is enabled and the switcher is also enabled if the en/psv and vdd are above their threshold. the table below summarizes the function of enl and en/psv pins. en/psv enl ldo switcher disabled low, < 0.4v off off enabled low, < 0.4v off on disabled 1.0v < high < 2.6v on off enabled 1.0v < high < 2.6v on off disabled high, > 2.6v on off enabled high, > 2.6v on on the enl pin also acts as the switcher under-voltage lockout for the v in supply. when SC401B is self-biased from the ldo and runs from the v in power source only, the v in uvlo feature can be used to prevent false uv faults for the pwm output by programming with a resistor divider at the vin, enl and agnd pins. when SC401B has an external bias voltage at vdd and the enl pin is used to program the v in uvlo feature, the voltage at fbl needs to be higher than 750mv to force the ldo of. timing is important when driving enl with logic and not implementing v in uvlo. the enl pin must transition from high to low within 2 switching cycles to avoid the pwm output turning off. if enl goes below the vin uvlo threshold and stays above 1v, then the switcher will turn of but the ldo will remain on. ldo start-up before start-up, the ldo checks the status of the following signals to ensure proper operation can be maintained. enl pin v in input voltage when the enl pin is high and v in is above the uvlo point, the ldo will begin start-up. during the initial phase, when the v dd voltage (which is the ldo output voltage) is less than 0.75v, the ldo initiates a current-limited start-up (typically 65ma) to charge the output capacitors while protecting from a short circuit event. when v dd is greater than 0.75v but still less than 90% of its final value (as sensed at the fbl pin), the ldo current limit is increased to ~115ma. when v dd has reached 90% of the fnal value (as sensed at the fbl pin), the ldo current limit is increased to ~200ma and the ldo output is quickly driven to the nominal value by the internal ldo regulator. it is recom - mended that during ldo start-up to hold the pwm switching of until the ldo has reached 90% of the fnal value. this prevents overloading the current-limited ldo output during the ldo start-up. 1. 2. applications information (continued)
SC401B 22 due to the initial current limitations on the ldo during power up (figure 10), any external load attached to the vdd pin must be limited to less than the start up current before the ldo has reached 90% of its fnal regulation value. v vldo final 90 % of v vldo final constant current startup @ ~ 115 ma voltage regulating with ~ 200 ma current limit short - circuit protection @ ~ 65 ma 0 . 7 v figure 10 ldo start-up ldo switch-over operation the SC401B includes a switch-over function for the ldo. the switch-over function is designed to increase efciency by using the more efcient dc-dc converter to power the ldo output, avoiding the less efficient ldo regulator when possible. the switch-over function connects the vdd pin directly to the vout pin using an internal switch. when the switch-over is complete the ldo is turned of, which results in a power savings and maximizes efciency. if the ldo output is used to bias the SC401B, then after switch-over the device is self-powered from the switching regulator with the ldo turned of. the switch-over starts 32 switching cycles after pgood output goes high. the voltages at the vdd and vout pins are then compared; if the two voltages are within 300mv of each other, the vdd pin connects to the vout pin using an internal switch, and the ldo is turned off. to avoid unwanted switch-over, the minimum diference between the voltages for vout and vdd should be 500mv. it is not recommended to use the switch-over feature for an output voltage less than vdd uvlo threshold since the SC401B is not operational below that threshold. switch-over mosfet parasitic diodes the switch-over mosfet contains parasitic diodes that are inherent to its construction, as shown in figure 11. if the voltage at the vout pin is higher than vdd, then the respective diode will turn on and the current will flow through this diode. this has the potential of damaging the device. therefore, v out must be less than vdd to prevent damaging the device. switchover mosfet parasitic diode vdd ldo v out switchover control figure 11 switch-over mosfet parasitic diodes design procedure when designing a switch mode supply the input voltage range, load current, switching frequency, and inductor ripple current must be specifed. the maximum input voltage (v inmax ) is the highest speci - fed input voltage. the minimum input voltage ( v inmin ) is determined by the lowest input voltage after evaluating the voltage drops due to connectors, fuses, switches, and pcb traces. the following parameters defne the design. nominal output voltage (v out ) static or dc output tolerance transient response maximum load current (i out ) ? ? ? ? applications information (continued)
SC401B 23 applications information (continued) there are two values of load current to evaluate con - tinuous load current and peak load current. continuous load current relates to thermal stresses which drive the selection of the inductor and input capacitors. peak load current determines instantaneous component stresses and fltering requirements such as inductor saturation, output capacitors, and design of the current limit circuit. the following values are used in this design. v in = 12v + 10% v out = 1.5v + 4% vdd = 5v f sw = 300khz load = 15a maximum frequency selection selection of the switching frequency requires making a trade-of between the size and cost of the external flter components (inductor and output capacitor) and the power conversion efciency. the desired switching frequency is 300khz which results from using components selected for optimum size and cost. a resistor (r ton ) is used to program the on-time (indirectly setting the frequency) using the following equation. sw ton f pf 25 k r u sw inmax out on f v v t u use the value associated with maximum v in for t on . t on = 379 ns at 13.2v in , 1.5v out , 300khz substituting for r ton results in the following solution. r ton = 133.3k?, use r ton = 130k? inductor selection in order to determine the inductance, the ripple current must frst be defned. low inductor values result in smaller size but create higher ripple current which can reduce ? ? ? ? ? efciency. higher inductor values will reduce the ripple current/voltage and for a given dc resistance are more efcient. however, larger inductance translates directly into larger packages and higher cost. cost, size, output ripple, and efciency are all used in the selection process. the ripple current will also set the boundary for psave operation. the switching will typically enter psave mode when the load current decreases to 1/2 of the ripple current. for example, if ripple current is 4a then psave operation will typically start for loads less than 2a. if ripple current is set at 40% of maximum load current, then psave will start for loads less than 20% of maximum current. the inductor value is typically selected to provide a ripple current that is between 25% to 50% of the maximum load current. this provides an optimal trade-of between cost, efciency, and transient performance. during the on-time, voltage across the inductor is (v in - v out ). the equation for determining inductance is shown next. ripple on out in i t ) v v ( l u example in this example, the inductor ripple current is set equal to 30% of the maximum load current. therefore ripple current will be 30% x 15a or 4.5a. to fnd the minimum inductance needed, use the v in and t on values that corre - spond to v inmax . h 99 . 0 a 5 . 4 ns 379 ) 5 . 1 2 . 13 ( l p u a slightly larger value of 1h is selected. this will decrease the maximum i ripple to 4.43a. note that the inductor must be rated for the maximum dc load current plus 1/2 of the ripple current.
SC401B 24 applications information (continued) the ripple current under minimum v in conditions is also checked using the following equations. ns 451 v v r pf 25 t inmin out ton vinmin _ on u u l t ) v v ( i on out in ripple u a 19 . 4 h 1 ns 451 ) 5 . 1 8 . 10 ( i vinmin _ ripple p u capacitor selection the output capacitors are chosen based upon required esr and capacitance. the maximum esr requirement is controlled by the output ripple requirement and the dc tolerance. the output voltage has a dc value that is equal to the valley of the output ripple plus 1/2 of the peak-to- peak ripple. a change in the output ripple voltage will lead to a change in dc voltage at the output. the design goal for output voltage ripple is 3% of 1.5v or 45mv. the maximum esr value allowed is shown by the following equations. a 43 . 4 mv 45 i v esr ripplemax ripple max esr max = 10.2 m? the output capacitance is usually chosen to meet tran - sient requirements. a worst-case load release, from maximum load to no load at the exact moment when inductor current is at the peak, determines the required capacitance. if the load release is instantaneous (load changes from maximum to zero in < 1s), the output capacitor must absorb all the inductors stored energy. this will cause a peak voltage on the capacitor according to the following equation. 2 out 2 peak 2 ripplemax out min v v i 2 1 i l cout ? 1 ? u assuming a peak voltage v peak of 1.65v (150mv rise upon load release), and a 10a load release, the required capaci - tance is shown by the next equation. 2 2 2 min 5 . 1 65 . 1 43 . 4 2 1 10 h 1 cout ? 1 ? u p cout min = 316f during the load release time, the voltage cross the induc - tor is approximately -v out . this causes a down-slope or falling di/dt in the inductor. if the load di/dt is not much faster than the di/dt of the inductor, then the inductor current will tend to track the falling load current. this will reduce the excess inductive energy that must be absorbed by the output capacitor, therefore a smaller capacitance can be used. the following can be used to calculate the needed capaci - tance for a given di load /dt. peak inductor current is shown by the next equation. i lpk = i max + 1/2 x i ripplemax i lpk = 10 + 1/2 x 4.43 = 12.215a dt dl current load of change of rate load i max = maximum load release = 10a out pk load max out lpk lpk out v v 2 dt dl i v i l i c u u u example s 1 a 5 . 2 dt dl load p this would cause the output current to move from 10a to 0a in 4s, giving the minimum output capacitance requirement shown in the following equation. 5 . 1 65 . 1 2 s 1 5 . 2 10 5 . 1 215 . 12 h 1 215 . 12 c out p u u p u c out = 169 f
SC401B 25 applications information (continued) note that c out is much smaller in this example, 169f compared to 316f based on a worst-case load release. to meet the two design criteria of minimum 316f and maximum 10.2m ? esr , select one capacitor of 330f and 9m ? esr . electrolytic capacitors have parasitic inductance or equiv - alent series inductance (esl). this esl increases the peak to peak magnitude of the output voltage ripple. therefore, it is recommended that an additional small ceramic capacitor be placed in parallel with c out in order to flter high frequency switching noise. as a result of the combi - nation of the electrolytic capacitors esl and the ceramic capacitor, the output votlage ripple can take a resonant form instead of the ideal triangle shape. if the esl value is high, it can cause cycle by cycle variation in the converter switching frequency. the capacitor manufacturers usually include the impedance vs frequency curve in their data - sheets. for example, eef-sx0e331er from panasonic or 4tpe220mf from sanyo has typically 1.5nh at 10mhz. stability considerations unstable operation is possible with adaptive on-time con - trollers, and usually takes the form of double-pulsing or esr loop instability. double-pulsing occurs due to switching noise seen at the fb input or because the fb ripple voltage is too low. this causes the fb comparator to trigger prematurely after the 250ns minimum of-time has expired. in extreme cases the noise can cause three or more successive on-times. double-pulsing will result in higher ripple voltage at the output, but in most applications it will not afect opera - tion. this form of instability can usually be avoided by providing the fb pin with a smooth, clean ripple signal that is at least 10mvp-p, which may dictate the need to increase the esr of the output capacitors. it is also impera - tive to provide a proper pcb layout as discussed in the layout guidelines section. another way to eliminate doubling-pulsing is to add a small (~ 10pf) capacitor across the upper feedback resis - tor, as shown in figure 12. this capacitor should be left unpopulated until it can be confrmed that double-pulsing exists. adding the c top capacitor will couple more ripple into fb to help eliminate the problem. an optional con - nection on the pcb should be available for this capacitor. v out to fb pin r 2 r 1 c top figure 12 capacitor coupling to fb pin esr loop instability is caused by insufficient esr. the details of this stability issue are discussed in the esr requirements section. the best method for checking sta - bility is to apply a zero-to-full load transient and observe the output voltage ripple envelope for overshoot and ringing. ringing for more than one cycle after the initial step is an indication that the esr should be increased. esr requirements a minimum esr is required for two reasons. one reason is to generate enough output ripple voltage to provide 10mvp-p at the fb pin (after the resistor divider) to avoid double-pulsing. the second reason is to prevent instability due to insuf - cient esr. the on-time control regulates the valley of the output ripple voltage. this ripple voltage is the sum of the two voltages. one is the ripple generated by the esr, the other is the ripple due to capacitive charging and dis - charging during the switching cycle. for most applica - tions the minimum esr ripple voltage is dominated by the output capacitors, typically sp or poscap devices. for stability the esr zero of the output capacitor should be lower than approximately one-third the switching fre - quency. the formula for minimum esr is shown by the following equation. sw out min f c 2 3 sr e u u s u using ceramic output capacitors when the system is using high esr value capacitors, the feedback voltage ripple lags the phase node voltage by 90 degrees. therefore, the converter is easily stabilized.
SC401B 26 applications information (continued) when the system is using ceramic output capacitors, the esr value is normally too small to meet the above esr cri - teria. as a result, the feedback voltage ripple is 180 degrees from the phase node and behaves in an unstable manner. in this application it is necessary to add a small virtual esr network that is composed of two capacitors and one resistor, as shown in figure 13. r 1 r 2 fb pin c c c out l c l r l dcr d x v in + - v l figure 13 virtual esr ramp circuit the ripple voltage at fb is a superposition of two voltage sources: the voltage across c l and the output ripple voltage. they are defned in the following equations. 1 c r s ) 1 dcr / l s ( dcr i vc l l l l u u u sw l out f c 8 i v u ' ' figure 14 shows the magnitude of the ripple contribution due to c l at the fb pin. r 1 r 2 fb pin c c l c l r l dcr d x v in + - v l figure 14 fb voltage by cl voltage it is shown by the following equation. 1 c s r // r c s r // r vc vfbc c 2 1 c 2 1 l l u u u u u figure 15 shows the magnitude of the ripple contribution due to the output voltage ripple at the fb pin. r 1 r 2 fb pin c c c out l c l r l dcr v l v out r 1 r 2 v out c c fb pin c out figure 15 fb voltage by output voltage it is shown by the following equation. 2 c 1 2 out out r c s 1 // r r v v vfb u u ' ' the purpose of this network is to couple the inductor current ripple information into the feedback voltage such that the feedback voltage has 90 degrees phase lag to the switching node similar to the case of using standard high esr capacitors. this is illustrated in figure 16. v out lx i l fb contribution by c l fb contribution by output voltage ripple combined fb figure 16 fb voltage in phasor diagram
SC401B 27 applications information (continued) the magnitude of the feedback ripple voltage, which is dominated by the contribution from c l , is controlled by the values of r 1 , r 2 and c c . if the corner frequency of (r 1 // r 2 ) x c c is too high, the ripple magnitude at the fb pin will be smaller, which can lead to double-pulsing. conversely, if the corner frequency of (r 1 // r 2 ) x c c is too low, the ripple magnitude at fb pin will be higher. since the SC401B regulates to the valley of the ripple voltage at the fb pin, a high ripple magnitude is undesirable as it signifcantly impacts the output voltage regulation. as a result, it is desirable to select a corner frequency for (r 1 // r 2 ) x c c to achieve enough, but not excessive, ripple magnitude and phase margin. the component values for r 1 , r 2 , and c c should be calculated using the following procedure. select c l (typical 10nf) and r l to match with l and dcr time constant using the following equation. l l c dcr l r u select c c by using the following equation. sw 2 1 c f 2 3 r // r 1 c u s u u | the resistor values (r 1 and r 2 ) in the voltage divider circuit set the v out for the switcher. the typical value for c c is from 10pf to 1nf. dropout performance the output voltage adjustment range for continuous con - duction operation is limited by the fxed 250ns (typical) minimum of-time of the one-shot. when working with low input voltages, the duty-factor limit must be calcu - lated using worst-case values for on and of times. the duty-factor limitation is shown by the next equation. ) max ( off ) min ( on ) min ( on t t t duty the inductor resistance and mosfet on-state voltage drops must be included when performing worst-case dropout duty-factor calculations. system dc accuracy (v out controller) three factors afect v out accuracy: the trip point of the fb error comparator, the ripple voltage variation with line and load, and the external resistor tolerance. the error comparator ofset is trimmed so that under static condi - tions it trips when the feedback pin is 600mv, 1%. the on-time pulse from the SC401B in the design example is calculated to give a pseudo-fxed frequency of 300khz. some frequency variation with line and load is expected. this variation changes the output ripple voltage. because adaptive on-time converters regulate to the valley of the output ripple, ? of the output ripple appears as a dc regu - lation error. for example, if the output ripple is 50mv with v in = 6 volts, then the measured dc output will be 25mv above the comparator trip point. if the ripple increases to 80mv with v in = 17v, then the measured dc output will be 40mv above the comparator trip. the best way to mini - mize this efect is to minimize the output ripple. the use of 1% feedback resistors may result in up to 1% error. if tighter dc accuracy is required, 0.1% resistors should be used. the output inductor value may change with current. this will change the output ripple and therefore will have a minor efect on the dc output voltage. the output esr also afects the output ripple and thus has a minor efect on the dc output voltage. switching frequency variation the switching frequency varies with load current as a result of the power losses in the mosfets and dcr of the inductor. for a conventional pwm constant-frequency converter, as load increases the duty cycle also increases slightly to compensate for ir and switching losses in the mosfets and inductor. an adaptive on-time converter must also compensate for the same losses by increasing the effective duty cycle (more time is spent drawing energy from v in as losses increase). the on-time is essen - tially constant for a given v out /v in combination, to ofset the losses the of-time will tend to reduce slightly as load increases. the net effect is that switching frequency increases slightly with increasing load.
SC401B 28 applications information (continued) pcb layout guidelines the optimum layout for the SC401B is shown in figure 17. this layout shows an integrated fet buck regulator with a maximum current of 15a. the total pcb area is approxi - mately 25 x 29 mm with single side components. critical layout guidelines the following critical layout guidelines must be followed to ensure proper performance of the device. ic decoupling capacitors pgnd plane agnd island fb, vout, and other analog control signals c ss bst, ilim, and lx c in and c out placement and current loops ? ? ? ? ? ? ? ic decoupling capacitors a 1 f capacitor must be located as close as pos - sible to the ic and directly connected to pins 3 (vdd) and 4 (agnd). another 1 f capacitor must be located as close as possible to the ic and directly connected to pins 3 (vdd) and pgnd plane. pgnd plane pgnd requires its own copper plane with no other signal traces routed on it. copper planes, multiple vias and wide traces are needed to connect pgnd to input capacitors, output capacitors, and the pgnd pins on the ic. the pgnd copper area between the input capacitors, output capacitors and pgnd pins must be as tight and compact as possible to reduce the area of the pcb that is exposed to noise due to current fow on this node. ? ? ? ? ? vout plane on top and bottom layer l c in c s s rfb 2 rfb 1 r i l i m c b s t lx plane on top and bottom layer all components shown top side agnd plane on inner layer v in plane on top and / or bottom layer rgnd agnd connects to pgnd close to ic pin 1 marking ic with vias for lx , agnd , vin c out pgnd on inner or bottom layer vout sense trace on inner layer vdd decoupling capacitor v d d cer . c in sp or poscap r t o n ctop pgnd on top layer r g n d figure 17 pcb layout
SC401B 29 agnd island agnd should have its own island of copper with no other signal traces routed on this layer that connects the agnd pins and pad of the ic to the analog control components. all of the components for the analog control cir - cuitry should be located so that the connections to agnd are done by wide copper traces or vias down to agnd. connect pgnd to agnd with a short trace or 0 ? resistor. this connection should be as close to the ic as possible. fb, vout, and other analog control signals the connection from the v out power to the analog control circuitry must be routed from the output capacitors and located on a quiet layer. the traces between vout and the analog control circuitry (vout, and fb pins) must be wide, short and routed away from noise sources, such as bst, lx, vin, and pgnd between the input capacitors, output capacitors, and the ic. the feedback components for the switcher and the ldo need to be as close to the fb and fbl pins of the ic as possible to reduce the possibil - ity of noise corrupting these analog signals. bst, ilim, ton, ss and lx the connections for the boost capacitor between the bst and lxbst must be short, wide and directly connected. ilim and ton nodes must be as short as possible to ensure the best accuracy in current limit and on time. r ilim should be close to the ic and connected between lxs (pin 28) and ilim (pin 27) only. r ton should be close to the ic and connected between ton (pin 31) and agnd (pin 30). ? ? ? ? ? ? ? ? ? ? c soft should be close to the ic and kept away from the boost capacitor. connect the agnd end of c soft to the agnd plane at pin 4. the lx node between the ic and the inductor should be wide enough to handle the inductor current and short enough to eliminate the pos - sibility of lx noise corrupting other signals. multiple vias should be used on the lx pad to provide good thermals and connection to an internal or bottom layer lx plane. capacitors and current loops figure 17 shows the placement of input/output capacitors and inductor. this placement shows the smallest current loops between the input/ output capacitors, the SC401B and the inductor to reduce the ir drop across the copper. ? ? ? ? applications information (continued)
SC401B 30 outline drawing mlpq-5x5-32 b aaa c c seating plane 1 2 n bbb c a b coplanarity applies to the exposed pad as well as the terminals . controlling dimensions are in millimeters ( angles in degrees ). notes : 2 . 1 . a pin 1 indicator ( laser mark ) d e a 2 bxn a a 1 e lxn e 1 0 . 76 0 . 76 3 . 48 1 . 05 d 1 1 . 66 1 . 49 pin 1 identification r 0 . 20 3 . 61 millimeters 0 . 50 bsc . 002 - 0 . 00 . 000 a 1 . 193 . 193 . 135 . 076 . 012 . 007 e 1 aaa bbb n e l a 2 d 1 d e b . 020 bsc . 137 . 016 . 003 . 004 32 . 197 (. 008 ) . 078 . 197 . 010 - 3 . 43 . 139 . 020 0 . 30 . 201 . 201 . 080 - . 012 4 . 90 4 . 90 1 . 92 - 0 . 18 . 031 min dim a max dimensions inches - nom . 039 0 . 80 min - 0 . 05 5 . 10 5 . 10 3 . 53 2 . 02 0 . 50 0 . 30 3 . 48 0 . 40 0 . 10 0 . 08 32 5 . 00 ( 0 . 20 ) 1 . 97 5 . 00 0 . 25 - 1 . 00 max - nom
SC401B 31 1 . 74 3 . 48 h 2 k 3 . 61 h 1 k 1 y h ( c ) g this land pattern is for reference purposes only . consult your manufacturing group to ensure your notes : 2 . dim x y h k p c g millimeters inches ( 4 . 95 ) . 012 . 030 . 165 . 020 . 078 . 137 (. 195 ) 0 . 30 0 . 75 3 . 48 0 . 50 1 . 97 4 . 20 dimensions company ' s manufacturing guidelines are met . 5 . 70 . 224 z failure to do so may compromise the thermal and / or functional performance of the device . shall be connected to a system ground plane . thermal vias in the land pattern of the exposed pad 3 . 4 . square package - dimensions apply in both x and y directions . controlling dimensions are in millimeters ( angles in degrees ). 1 . x p z h 1 . 059 1 . 49 h 2 . 065 1 . 66 k 1 . 041 1 . 05 1 . 74 land pattern mlpq-5x5-32
SC401B 32 contact information semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111 fax: (805) 498-3804 www.semtech.com ? semtech 2011 all rights reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any conse - quence of its use. publication thereof does not convey nor imply any license under patent or other industrial or intellec - tual property rights. semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specifed maximum ratings or operation outside the specifed range. semtech products are not designed, intended, authorized or warranted to be suitable for use in life- support applications, devices or systems or other critical applications. inclusion of semtech products in such applications is understood to be undertaken solely at the customers own risk. should a customer purchase or use semtech products for any such unauthorized application, the customer shall indemnify and hold semtech and its ofcers, employees, subsidiaries, afliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. notice: all referenced brands, product names, service names and trademarks are the property of their respective owners.

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